This invention relates to the fabrication of Vertical Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs), which provide improved threshold variation and offer channel length scalability superior to devices existing in the prior art.
In DRAM (Dynamic Random Access Memory) devices, a transfer MOSFET device is employed as a switch connected to the charge storing capacitor. A DRAM circuit usually includes an array of memory cells interconnected by rows known as wordlines and columns known as bitlines. Reading data from or writing data to a particular memory cell in the DRAM is achieved by simultaneously activating the combination of a selected wordline and a selected bitline. Different types of MOSFETs are used in DRAM circuits.
FIG. 1A is a fragmentary, schematic, vertical sectional elevational view of a prior art vertical, deep trench, MOSFET, DRAM cell 10 formed in a P− doped silicon substrate 15. The cell 10 includes a vertical MOSFET transistor 17 in which the plane of channel current flow is parallel to the primary surface of the P− doped silicon substrate 15. On the right side of cell 10, a deep trench DT has been formed in the substrate 15, with the right edge of the deep trench DT and the substrate 15 excluded from the view for convenience of illustration.
The MOSFET transistor 17, which is formed along the left sidewall of the deep trench DT includes a gate oxide layer 24 formed on the sidewall of the deep trench DT juxtaposed with a gate conductor (GC) 16 formed at the top of the trench DT. A capacitor C is formed in the lower portion of the deep trench DT.
The FET transistor 17 includes a drain region D, a source region S, and a channel CH. The drain region D is located in an N+ doped bit line diffusion (XA) region 26 on top of the substrate 15. The source region S is formed in an N+ doped outdiffusion region OD, which is juxtaposed with an N+ doped strap 13 formed in the deep trench DT, at the top of an N+ doped capacitor node 11. The channel CH of the FET transistor 17 is located in the P− doped substrate 15 to the left of the gate oxide layer 24 formed along the upper sidewall of the deep trench DT, with the channel region CH of transistor 17 located between the drain region D and the source region 5, from top to bottom. Thus the channel CH and the gate conductor 16 are separated, as stated above, by the thin gate oxide layer 24, which is formed on the sidewall of the deep trench DT with the drain region D at the top of the channel CH and the source region S at the bottom of the channel CH in the vertical transistor 17. The transistor 17 is turned on when the gate conductor (GC) 16 is raised to Vpp by electrical connection of wiring thereto (not shown) at the top of the GC 16.
In this vertical MOSFET transistor 17, the current flow is perpendicular with respect to the primary (i.e. horizontal as shown in FIG. 1) surface of the silicon substrate 15 through the channel CH between the source region S and the drain region D.
The deep trench capacitor C (comprising a three-dimensional structure), which is formed in the lower portion of the deep trench DT, is used as the charge storing capacitor C of the MOSFET cell 10. As will be well understood by those skilled in the art, such a deep trench capacitor C is normally formed by the process of etching vertical deep trenches DT of various dimensions into a semiconductor substrate, such as doped silicon substrate 15. As usual, the bottom of the deep trench DT contains N+ doped polysilicon, which serves as the storage node 11 of the capacitor C, with the storage node 11 comprising the inner plate of the capacitor C separated from the substrate 15 by dielectric layers 12/44. The bottom of the deep trench DT is shown with intermediate portions cut away near the bottom of FIG. 1A.
Prior to forming the storage node 11 of the capacitor C, an N+ doped region comprising the outer plate 42 of the capacitor is formed in the P− doped silicon substrate 15 deep trench DT when it is empty, i.e. before forming the storage node 11 by filling the deep trench DT with doped polysilicon. At that time, N+ dopant from a dopant source is introduced into the inside of the empty deep trench DT (with suitable masking as will be well understood by those skilled in the art). Then, when the N type dopant from the dopant source reaches the bottom of the deep trench DT, it is caused to diffuse therefrom outwardly from the bottom of the deep trench DT into the P− doped silicon substrate 15. In that way, an N+ doped outer plate 42 of the capacitor C is formed outside of the lower end of the deep trench DT, as indicated in FIG. 1A.
After forming the outer plate 42, a thin conformal layer of the storage node dielectric 44 is formed inside the deep trench DT on the exposed inner walls of the lower portion of the deep trench DT. Then a lower portion of the capacitor storage node 11 is formed inside the storage node dielectric 44. In short, the outer plate 42 surrounds the lower part of the deep trench DT, the storage node dielectric 44 and the lower portion of the capacitor storage node 11, in that order.
Above the level of the storage node dielectric 44, a LOCOS dielectric collar 12 is formed in the deep trench DT as a thin conformal layer (somewhat thicker than the storage node dielectric 44) on the outer walls of the deep trench DT. The collar 12 is far shorter than the capacitor C, which is shown on a reduced vertical scale for convenience of illustration.
The N+ doped polysilicon of the capacitor storage node 11 fills the deep trench DT inside storage node dielectric 44 and the capacitor dielectric collar 12 thereby completing formation of the capacitor C. A vertical trench transistor, such as transistor 17, can overcome the scalability limitations in planar transistors, since the channel length of the channel CH of transistor 17 is not defined and limited by lithography. A longer channel CH can be used to suppress the disadvantages of the short channel effect, which is a problem for planar transistors.
At the top surface of the cell 10, the N+ doped bit line diffusion (XA) region 26 (which is the drain region D) is formed in the top surface of the P− doped silicon substrate 15. A bitline contact 28 makes contact with the top surface of the XA region 26.
As indicated above, the source region S of transistor 17 comprises an N+ doped, buried-strap, out-diffusion region OD. The buried-strap, out-diffusion region OD is formed by out-diffusion of N type dopant from the N+ doped buried strap 13 at the top of the capacitor storage node 11, in a conventional process as will be well understood by those skilled in the art.
The collar 12 consisting of a dielectric such as silicon oxide helps to shut off the parasitic leakage path from the capacitor storage node 11 to the buried plate 42 outside the deep trench DT, the storage node dielectric 44 and the collar 12. A Trench Top Oxide (TTO) layer 14 isolates the capacitor storage node 11 from the N+ doped polysilicon of the gate conductor (GC) 16.
The vertical pass transistor cell 10 of FIG. 1A provides an attractive alternative to conventional, planar, DRAM pass transistor design and scaling. As stated above, the short channel effect is suppressed since a longer device effective channel length can be used which is not defined by lithography. The drive current is not impacted because two pass transistors 17 (only one of which is shown for convenience of illustration) are used in parallel to drive the storage capacitor C. The incorporation of the third dimension which is implicit in the vertical transistor design allows great flexibility in designing DRAM pass transistors 17 that are optimized for DRAM operations. However, there are concerns that need to be addressed as well.
One of the problems with previous designs of the vertical pass transistors 17 was that there was a large substrate bias effect that degraded the write back current. A graded doping profile in the direction perpendicular to the channel CH is required to achieve a small substrate bias effect. In the planar pass transistor design, this is naturally achieved with a blanket Vt adjustment implant.
In the vertical pass transistor cell 10 of FIG. 1A, a similar blanket implant illustrated by implanting dopant 32 in FIG. 1B leads to laterally uniform doping and hence high substrate sensitivity of the P− doped silicon substrate 15. In FIG. 1B, the gate electrode 16 is masked by an array top oxide 29 and the P− type dopant 32 is ion implanted vertically into the channel region CH to provide a Vt adjustment implant therein. The dopant is implanted directly into the channel region CH vertically and is therefore laterally uniform.
FIG. 2A illustrates a prior art angled ion implantation approach to solving the problem illustrated by FIGS. 1A and 1B, wherein the device structure and the Vt adjustment implant for improved substrate sensitivity and write back current are enhanced by angled ion implantation of boron ions 32 implanted diagonally at an angle θ with respect to the vertical (normal to the top surface of the cell 10) by ion implantation. During the angled ion implantation of ions 32, the bit line diffusion (XA) region 26 is shown as being protected from implantation of ions 32 by a masking layer 59.
FIG. 2A illustrates a solution to the problem of the process of FIG. 1B, which is to perform on the cell 10 of FIG. 1A, an angled Vt adjustment ion implantation of P type dopant ions into and through a recessed gate conductor 16 composed of N+ doped polysilicon.
In FIG. 2A, a prior art approach is used, in an attempt to achieve the desired doping profile. The P− type dopant ions 32 are implanted through the recess R by angled ion implanting ions 32 of P− type dopant at an angle θ into the corner of the channel CH partially through the recessed polysilicon of the gate conductor GC 16 into the channel CH. To achieve a successful dopant profile in the channel CH, gate conductor 16 must have been recessed to the correct depth by etching away a portion of N+ doped polysilicon fill to form a recess R. The problem associated with this approach is that the location of the peak of the implanted P− type dopant 32 is defined by the depth of the recess R formed by recessing the polysilicon of the GC 16, which has significant process variation. The junction with the bitline diffusion (XA) region 26 is thus not self-aligned to the gate conductor 16.
Ideally, the P− type doping into the channel CH should peak just below the junction 25 between bitline diffusion (XA) region 26 and P− doped silicon substrate 15 to taper off in both lateral and vertical directions, as shown by the doping profiles 18/19 in FIG. 2B and FIG. 2C.
Referring to FIG. 2B, the cell 10 of FIG. 1A is shown after the process of angled ion implantation of P type dopant ions performed in FIG. 2A has resulted in lateral scattering of the implanted P type dopant atoms illustrated by a solid profile line 18P′ marked with a horizontal arrow. The scattering of the dopant atoms, combined with diffusion of the dopant atoms in the region of the channel CH and to the left thereof, creates a laterally graded profile 18P′ (from right to left) of P− type dopant as shown in FIG. 2B with a peak on the right near the gate oxide layer 24 trailing down to a low concentration to the left.
Referring to FIG. 2C, there is also a solid, vertically graded profile line of P− type dopant 18P″ produced by the process illustrated by FIG. 2A. The cell 10 is shown after the process of angled ion implantation of dopant atoms performed in FIG. 2A has resulted in vertical scattering of the implanted dopant atoms combined with diffusion in the region of the channel CH and therebelow, which creates a vertically graded profile 18P″ (from top to bottom) of P-type dopant atoms as shown in FIG. 2 (with a peak spaced on the right near the gate oxide layer 24 a preferred distance “m” below the line 25 at the bottom of the XA region 26 trailing down to substantially lower concentrations thereabove and therebelow.
However, FIG. 2C also shows a hypothetical dotted profile line of a graded vertical profile of P− type dopant 18P″ caused by too shallow a recessing of the gate conductor 16. If the actual depth of the recessed gate conductor 16 is at the level of the hypothetical dotted line level 30, a distance n above the level 40, then as shown by the dotted line curve 18P″ in FIG. 2C, the result will be that the maximum of the vertical profile of the P− type dopant will be only the distance m−n below the line 25, which is too close to the lower boundary 25 of the XA region 26. That is undesirable since the Vt implant will be too high, i.e. in too close proximity to the drain region D in XA region 26, and P− type dopant will be compensated by N+ dopant atoms in the region 26. Thus the deep trench vertical DRAM processes can be faced with additional Vt variation due to problems in controlling the actual depth of the gate recess level 40.
Accordingly, due to process variations it can be expected that the hypothetical excessively high gate recess level 30 can be produced during manufacturing due to process variations and channel length scaling challenges. In summary, the dotted line gate recess level 40 is acceptable, but the gate recess level 30 is at an unacceptably high level. The problem is what to do to avoid this result.
FIG. 2D shows a desirable composite “three-dimensional” profile 18P″ (vertical and horizontal distribution) of the concentration levels of the P type dopant atoms implanted in the step illustrated by FIG. 2A with the gate conductor 16 recessed to the level 40 shown in FIGS. 2A and 2B. This illustrates a desirable distribution of the dopant. However, that is only because the gate conductor 16 has been recessed sufficiently, as desired, unlike the unacceptable result shown by the profile 18″ in FIGS. 2C and 2E.
As in FIG. 2C, FIG. 2E shows the undesirable profile 18P″ in the form of a composite “three-dimensional” (vertical and horizontal distribution) of the concentration levels of the P type dopant atoms implanted in the step illustrated by FIG. 2A, but with the gate conductor 16 recessed to the hypothetical dotted line level 30 at which the gate recess level 30 is at an unacceptably high level.
As shown by the doping profile 18″ in FIGS. 2C and 2E, if a GC recess 30 of GC 16 is too shallow, a significant portion of the P− type doping profile 19 is compensated by diffusion of the P type dopant 32, directly leading to a device threshold voltage drop. In such a design regime, in order to maintain a low value of sub-threshold leakage current, the designer is forced to raise the nominal Vt thereby degrading nominal drive current. If nominal Vt were kept the same, the P− type doping would be required to be placed deeper to minimize compensation by XA diffusion. However, the tail of the P− type dopant ion should not touch the strap out-diffusion OD, which would cause elevated junction leakage. As a result, the node diffusion defined by another recess needs to be deeper as well. In other words, the device channel length cannot be scaled to increase the drive current. This invention provides a means of reducing Vt variation and enabling further device channel length scaling in vertical trench MOSFETs.
Commonly assigned U.S. Pat. Nos. 6,414,347 and 6,440,793 of Ramachandra Divakaruni et al. entitled “Vertical MOSFET” describe making a vertical MOSFET structure by the following steps. Provide a vertical MOSFET DRAM cell structure having a deposited Gate Conductor (GC) layer planarized to a top surface of a Trench Top Oxide (TTO) on the overlying silicon substrate. Form a recess in the GC layer below the top surface of the silicon substrate. Implant N-type dopant species through the recess at an angle to form doping pockets in the array P-well. Deposit an oxide layer into the recess and etch the oxide layer to form spacers on sidewalls of the recess. Then deposit a GC material into the recess and planarize the GC to the top surface of the TTO.
Copending, commonly assigned, U.S. patent application of Dureseti Chidambarrao et al. entitled “Vertical MOSFET with Horizontally Graded Channel Doping”, Ser. No. 10/096,219; filed 11 Mar. 2002, now U.S. Pat. No. 6,740,920 describes body effects in vertical MOSFET transistors which are considerably reduced with other device parameters unaffected wherein the vertical transistor has a threshold implant with a peak at the gate and an implant concentration distribution that declines rapidly away from the gate to a plateau having a low P-well concentration value. In one embodiment two body implants both of which involve counterdoping are employed with an angled ion implantation having a peak at the gate that sets the Vt and a laterally uniform low dose implant that sets the well dopant concentration.
“Vertical Pass Transistor Design For Sub-100 nm DRAM Technologies” K. McStay et al, VLSI Technical Digest; Proceedings of 2002 Symposium on VLSI Technology, Section 8-3, pages 180-181, Jun. 11, 2002.